A. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device such as a reverse blocking IGBT (IGBT: insulated gate bipolar transistor). In particular, the invention relates to a manufacturing method whereby a separation layer of a reverse blocking IGBT is formed.
B. Description of the Related Art
FIGS. 18A to 18C, showing a heretofore known reverse blocking IGBT manufacturing method, are main portion manufacturing step sectional views shown in order of step. Herein, a reverse blocking IGBT with a blocking voltage of 1,200V is given as an example.
In FIG. 18A, front surface 92 of silicon wafer 91a (hereafter called simply “the wafer 91a”) with a thickness in the region of 400 μm is covered with mask 95 having apertures 96. Continuing, an impurity source (for example, a boron source) is applied to mask 95, and a long-time diffusion in the region of 300 hours is carried out at a high temperature of, for example, 1,300° C. Owing to the long-time diffusion, the impurity is introduced into wafer 91a through apertures 96, and thermal diffusion layers 97 exceeding 200 μm are formed.
Next, in FIG. 18B, surface structure 98 of a planar gate type reverse blocking IGBT is constructed on front surface 92 of wafer 91a. As shown in FIG. 19, surface structure 98 is configured of p-well layer 101, n-emitter layer 102, gate insulating film 103, gate electrode 104, interlayer insulating film 105, emitter electrode 106, and surface protecting film 107 of polyimide or the like. FIG. 19 is a detailed view of an E portion of FIG. 18B. Also, surface protecting film 107 is not shown in FIG. 18B.
Next, in FIG. 18C, the top of surface structure 98 is covered with resist 99 in order to protect surface structure 98. Continuing, back surface 93a of wafer 91a is ground by in the region of 200 μm so as to reach thermal diffusion layers 97, forming a thinned wafer 91. In this way, thermal diffusion layers 97 are continuous from the front to the back, and separation layers 100 of the reverse blocking IGBT are formed.
Also, in JP-A-2001-185727 (FIG. 27), it is described that, after a p-diffusion layer is formed on the front surface and a p-collector layer is formed on the back surface, grooves are formed by a machining and a chemical process from the back surface in such a way as to come into contact with the front surface p-diffusion layer, and the p-diffusion layer is formed on the side walls of the grooves and used as a separation layer. In this case, the p-collector layer and the p-diffusion layer formed on the side walls of the grooves are formed separately.
Also, in JP-A-2006-303410 (FIG. 1) and WO-2009-139417 (FIG. 1), it is described that, after separation grooves are formed from the back surface in such a way as to come into contact with a front surface diffusion layer, a p-diffusion layer formed in the grooves and a p-collector layer formed on the back surface are formed simultaneously.
Also, in JP-A-2005-93972 (FIG. 2), after forming a p-collector layer, grooves are formed in such a way as to make contact with the p-collector layer. It is described that a p-diffusion layer is formed on the side walls of the grooves and used as a separation layer. In this case, a thin p-layer forming the collector layer and a deep p-layer formed on the side walls of the grooves are formed separately.
Also, in JP-A-2004-336008 (FIG. 1), it is described that grooves are formed after a p-collector layer is formed, an impurity is diffused from the grooves, and this diffusion layer is linked to the p-collector layer and used as a separation layer. The separation layer is formed farther to the inside of the chip than the dicing line.
Also, in JP-A-2009-177039 (FIG. 7), an ion implantation is carried out into the back surface, forming a p-collector layer, and then the wafer is diced into chips. It is described that the chips are stacked together, and an ion implantation is carried out into a side surface thereof, forming a separation layer.
With the heretofore known manufacturing method shown in FIGS. 18A to 18C, as separation layers 100 are formed only by a thermal diffusion of an impurity diffusion from front surface 92, it is difficult to form thick separation layers, and it is difficult to increase the blocking voltage of the device. As previously described, with the 1,200V class, the thickness of wafer 91 is in the region of 200 μm, and in order to form the thick separation layers 100, a long-time thermal diffusion of in the region of 300 hours at a high temperature in the region of 1,300° C. is necessary. When carrying out a long-time thermal diffusion at this kind of high temperature, oxygen enters the high resistance wafer necessary for an increase in blocking voltage. The oxygen becomes a donor, reducing the resistance, and causing a disadvantage such as a reduction in the blocking voltage of the reverse blocking IGBT.
Also, as a long time in the region of 300 hours (approximately two weeks) is necessary for one thermal process, throughput is extremely poor, leading to a reduction in productivity. Next, problems with the previously described JP-A-2001-185727 (FIG. 27), JP-A-2006-303410 (FIG. 1), WO-2009-139417 (FIG. 1), JP-A-2005-93972 (FIG. 2), JP-A-2004-336008 (FIG. 1), and JP-A-2009-177039 (FIG. 7) will be described.
In JP-A-2001-185727 (FIG. 27), as the fabrication of the grooves is carried out by a machining and a chemical process, there is no description of an anisotropic etching utilizing the crystal orientation.
In JP-A-2006-303410 (FIG. 1) and WO-2009-139417 (FIG. 1), as the p-diffusion layer of the grooves and the p-collector layer are formed simultaneously, it is not possible to optimize both the impurity concentration of the groove diffusion layer and the impurity concentration of the p-collector layer. For example, when the impurity concentration of the groove diffusion layer is optimized, the tradeoff between the turn-on voltage and switching loss deteriorates. Also, when the impurity concentration of the p-collector layer is optimized, it is difficult to ensure the blocking voltage. Also, as the grooves are formed from the back side to near the front surface, the mechanical strength of the wafer is low, and it may break when handling.
In JP-A-2005-93972 (FIG. 2), as deep grooves are formed from the front surface side reaching the p-collector layer on the back surface side, the mechanical strength of the wafer is low, and it may break when handling.
In JP-A-2004-336008 (FIG. 1), as the dicing line is on the outer side of the separation layer, the chips increase in size, and the chip cost increases.
In JP-A-2009-177039 (FIG. 7), as the chips are stacked after dicing and an ion implantation is carried out into a side surface thereof, it may happen that the surfaces of the chips are scratched, leading to a reduction in device performance.
Furthermore, in JP-A-2001-185727 (FIG. 27) to JP-A-2009-177039 (FIG. 7), there is no description to the effect that “Grooves are formed by an anisotropic etching with an alkaline solution from the back surface side in such a way as to come into contact with the thermal diffusion layers formed from the front surface side. Continuing, the thermal diffusion layers are formed on the inner walls of the grooves, and separation layers are formed from the thermal diffusion layers and in-groove diffusion layers. Furthermore, an ion implantation for forming the in-groove diffusion layers and an ion implantation for forming the back surface collector layer are carried out separately”.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.